The latest development in the electronics department, Ethernet has for the first time become the standard connection between the detectors and the Linux PCs in the PILTATUS3 generation of detectors, recently introduced by DECTRIS. The request for higher readout frame rates brought about the replacement of the GigaStar (1 Gbit/s) interface, which had been the previous standard. It has now been replaced by a 10 Gbit/s Ethernet interface. Future PILATUS3 detectors will come with up to four 10 Gbit Ethernet links. Even though not all of these links are being used at this time, the hardware will be ready to support even higher readout frequencies at a later point in time. The following two figures show the architecture of the PILATUS3 6M and 2M detectors.

Fig. 1: PILATUS3 6M detector architecture with 60 modules, 10 BCBes and two DCBes connected to two 10 Gbit/s links (each 50% load) towards the Detector PC.
Fig. 2: PILATUS3 2M detector architecture with 24 modules, four BCBes and one DCBe connected to two 10 Gbit/s links (each with a 50% load) towards the detector PC.

Latest FPGA Technology and High Speed Transceivers

FPGAs (Field-Programmable Gate Array) make up the central component for the processing of data coming from the sensors, and incorporate Firmware to control sequences and process data inside a detector. Compared to CPUs, FPGAs have the major advantage of being able to process data in parallel. This aspect makes these devices extremely powerful and thus well suited for handling the high data volume of DECTRIS detectors.

Summary of FPGA advantages:

  • High speed parallel data processing
  • High speed data transmission through high speed transceivers
  • Re-programmable and ready for firmware updates

Faster, more complex devices are under rapid development and are being released every year. DECTRIS aims to use the latest in FPGA technology to enable data to be processed as fast as possible and to increase image frame rates. A positive bonus effect: the FPGA technology (40 nm structures for Xilinx Virtex 6 FPGA) helps to keep power consumption low even while improving performance.

Fig. 3: BCBe board with a Xilinx Virtex-6 FPGA and SODIMM memory socket for data caching.

High speed transceivers (or SERDES, a serializer/deserializer) are at the heart of all today’s high bandwidth interfaces, including Ethernet, HDMI and DisplayPort video, USB 3.0 device interconnect, PCI-Express PC busses, and ESATA/SAS disk interfaces. By utilizing these high speed transceivers in its own hardware designs, DECTRIS is able to provide greater speed, density, and flexibility in its detector readout electronics. High speed transceivers can simplify the detector electronics since fewer interconnection signals are required, and they also allow more flexibility in the choice of high speed interconnect, such as board to board, or cable to board.

The following advantages were noted by DECTRIS when high speed transceivers were implemented as the new standard:

Argument Advantage DECTRIS
Much more tolerant against cable and circuit board conditions Standard cables may be used
High speed SERDES are essentially a 'black box' and include a variety of configuration options to adjust signal quality when needed. Reduction of development risks
No 'setup/hold' timing issues, only 'eye' opening matters. Potentially reduced developmental effort as third-party IPs can be used.
Reduced hardware complexity since significantly fewer signals are needed to achieve a higher data rate. Detectors become more modular, potentially available for custom applications with different detector image sizes or higher frame rates.

High speed transceivers are clearly the future of high speed data transmission and are under constant development at all well-known component suppliers.

DECTRIS strongly believes that by combining these two technologies (Ethernet and the latest FPGAs with high speed transceivers) the right platform has been chosen for the development of competitive detectors for the next decade.